Implementation of the Viterbi decoder in FPGA
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Keywords:
convolutional encoder, Viterbi decoder, FPGA, Spartan XC3S400A FPGA, path memory, register exchangeAbstract
It is well known that data transmissions over wireless channels are affected by attenuation, distortion, interference and noise, which affect the receiver’s capacity to receive correct information. Convolutional encoding with Viterbi decodingis a powerful method for forward error correction. It hasbeen widely deployed in many wireless communicationsystems to improve the limited capacity of thecommunication channels. In this article, we present a SpartanXC3S400A field-programmable gate array implementationof Viterbi Decoder with a constraint length of 3 and a coderate of 1/2. The Viterbi Decoder is compatible with manycommon standards, such as DVB, 3GPP2, 3GPP LTE, IEEE802.16, Hiperlan, and Intelsat IESS-308/309.
References
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2. Viterbi A.D., Omura Dzh.K. Printsipy tsifrovoy svyazi i kodirovaniya. – M.: Radio i svyaz', 1982. – 536 s. (in Russ)
3. Morelos-Saragosa R. Iskusstvo pomekhoustoychivogo kodirovaniya. Metody, algoritmy, primeneniya. – M.: Tekhnosfera, 2005. – 320 s. (in Russ)
4. Inyup Kang and Alan N. Wilson. Low Power Viterbi Decoder for CDMA Mobile Terminal // IEEE Journal of Solid State Circuits. - 2010. - Vol 33. - p.p. 473-481.
5. Viterbi A. J. Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm//IEEE Trans. Inform. Theory. – 1967. -Vol. IT-13. - pp. 260-269.
6. Muder D.J. Minimal trellises for Block codes//IEEE Transaction Information Theory. – 2009. - Vol34. - p.p.1049-1053.
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How to Cite
Sandybaev, E., Tuenbayev, O., & Imanbayeva, A. (2014). Implementation of the Viterbi decoder in FPGA. Recent Contributions to Physics (Rec.Contr.Phys.), 48(1), 68–73. Retrieved from https://bph.kaznu.kz/index.php/zhuzhu/article/view/761
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Section
Nonlinear Physics. Radiophysics
